9 Memory Barrier Transfer register, MBT

Triggers a barrier transaction on the AXI interface. The write access on the APB slave interface is complete when the barrier transaction completes on the AXI interface. Until then, pready_s is held low. When the barrier transaction completes, TrgBarTran is cleared to 0. If another barrier transaction is required then you must write 1 to TrgBarTran again. If the TrgBarTran is already 1, then this write has no effect. It indicates that a barrier transaction is already in progress and has not completed. This is possible if an abort request aborted the earlier transaction on the APB slave interface, and a new request to issue a barrier transaction is requested. This results in an error response from the AXI-AP, if the barrier transaction is still not complete.

The MBT register characteristics are:

Attributes
Offset

0x0D20

Type

Read-write

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-95 MBT register bit assignments
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The following table shows the bit assignments.

Table 9-99 MBT register bit assignments

Bits Reset value Name Function
[31:3] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[2:1] 0b00 BarTran

Barrier transactions.

0x0

Barrier with normal access.

0x1

Memory barrier.

0x2

Reserved.

0x3

Synchronization Barrier.

[0] 0b0 TrgBarTran

This bit triggers barrier transactions when written to 1.

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