|Home > Programmers model > css600_axiap introduction > Register descriptions > Memory Barrier Transfer register, MBT|
Triggers a barrier transaction on the AXI interface. The write access on the APB slave interface is complete when the barrier transaction completes on the AXI interface. Until then, pready_s is held low. When the barrier transaction completes, TrgBarTran is cleared to 0. If another barrier transaction is required then you must write 1 to TrgBarTran again. If the TrgBarTran is already 1, then this write has no effect. It indicates that a barrier transaction is already in progress and has not completed. This is possible if an abort request aborted the earlier transaction on the APB slave interface, and a new request to issue a barrier transaction is requested. This results in an error response from the AXI-AP, if the barrier transaction is still not complete.
The MBT register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-99 MBT register bit assignments
Read-As-Zero, Writes Ignored.
This bit triggers barrier transactions when written to 1.