4 Trace Memory Controller

The css600_tmc Trace Memory Controller (TMC) is used for capturing trace data into local or system memory, or streamed to a High Speed Serial Trace port. The trace can be read by an off-chip external debugger, or by on-chip self-hosted debug software.

The TMC can be configured into the following configurations:

Embedded Trace Buffer (ETB)

Enables trace to be stored in a dedicated SRAM that is used as a circular buffer.

The following figure shows the external connections on the TMC ETB configuration.

Figure 4-10 css600_tmc_etb logical connections
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Embedded Trace FIFO (ETF)

Enables trace to be stored in a dedicated SRAM, used either as a circular buffer or as a FIFO. The functionality of the ETF configuration is a superset of the functionality of the ETB configuration. In a CoreSight™ system, the ETF can be inserted anywhere on the trace bus and used as a FIFO to smooth out a bursty trace.

The following figure shows the external connections on the TMC ETF configuration.

Figure 4-11 css600_tmc_etf logical connections
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Embedded Trace Router (ETR)

Enables trace to be routed over an AXI interface to the system memory or to any other AXI slave.

The following figure shows the external connections on the TMC ETR configuration.

Figure 4-12 css600_tmc_etr logical connections
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Embedded Trace Streamer (ETS)

Enables trace to be routed over an AXI4-Stream interface to a streaming device such as an HSSTP link layer, either directly or through an AXI4 Stream interconnect. ETS retains a subset of the ETR feature set, and removes those features not required for the streaming application, and provides a lower gate count than ETR uses for streaming.

The following figure shows the external connections on the TMC ETS configuration.

Figure 4-13 css600_tmc_ets logical connections
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The TMC can be programmed to capture trace in four different modes:

Circular Buffer modeThis mode is available in ETB, ETF, and ETR TMC configurations. TMC captures trace using its storage as a circular buffer, overwriting old trace when the buffer is full. No trace is output until capture is complete. In this mode, trace capture can automatically stop after receiving a trigger signal.
Hardware Read FIFO modeThis mode is available only in the ETF configuration. TMC uses its storage as a FIFO, acting as a link between a trace source and a trace sink. No trace is lost or overwritten, and backpressure is applied through the AMBA Trace Bus (ATB) to the trace source when the FIFO becomes full. Most trace sources eventually overflow when subject to backpressure for a long time, but it is always the trace sources that lose trace, not the ETF. This mode enables large bursts of trace to be smoothed, reducing the need to exert backpressure, so that:
  • Trace can be output over a trace port using fewer pins than would be required without the ETF, by smoothing peaks in trace bandwidth over long periods.
  • A subsequent ETR receiving trace through ETF can cope with large delays that are introduced by higher priority masters on the AXI interconnect without losing the trace.
Software Read FIFO mode 1Software Read FIFO mode 1: This mode is available in ETB, ETF, and ETR configurations. In this mode, the component functions as a FIFO where data is read out by software over the Debug APB interface. This mode provides a low-speed communication channel for trace data, reusing the existing programming interface.
Software Read FIFO mode 2This mode is available only in ETR configuration. In this mode, the trace memory accessible through the AXI interface is used as a FIFO. The key difference from Software Read FIFO mode 1 is that the data is read out by the debugger directly from the memory, bypassing the ETR datapath. The memory read pointer is still managed by the ETR so the debugger must inform the ETR of the amount of trace extracted. The trace that is extracted from the memory can be output over a streaming interface, such as USB, which provides much higher bandwidth than the debug APB interface.
This section contains the following subsections:
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