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Home > Programmers model > css600_apbrom introduction > Register descriptions > ROM Entries register 2, ROMEntry2 |
Each register contains a descripter of a CoreSight component in the system. All ROM table entries conform to the same format.
The ROMEntry2 register characteristics are:
Offset |
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Type | Read-only |
Reset |
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Width | 32 |
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-173 ROMEntry2 register bit assignments
Bits | Reset value | Name | Function | ||||||||
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[31:12] | IMPLEMENTATION_DEFINED | BASE_ADDR | Base address of component. |
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[11:9] | IMPLEMENTATION_DEFINED | SBZ | Software should write the field as all 0s. |
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[8:4] | IMPLEMENTATION_DEFINED | POWER_DOMAIN_ID | Indicates the power domain ID of the component. Only valid if bit 2 is set. If bit 2 is clear then this field has a value of 0. Possible values are 0 to 31, representing the 32 DBGPWRUPREQ/ACK interface pins of the component. |
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[3] | IMPLEMENTATION_DEFINED | SBZ | Software should write the field as all 0s. |
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[2] | IMPLEMENTATION_DEFINED | POWER_DOMAIN_ID_VALID | Indicates whether there is a power domain ID specified in the ROM table entry.
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[1:0] | IMPLEMENTATION_DEFINED | PRESENT | Indicates whether the ROM table entry is present.
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