2 AXI transfers

The AMBA4 AXI-compliant Master Port supports:

  • Bursts of single transfer.
  • No out-of-order transactions.
  • No issuing of multiple outstanding addresses.
  • Master processes one transaction at a time in the order they are issued.
Burst length

The AXI-AP supports a burst length of one transfer only. ARLEN[3:0] and AWLEN[3:0] are always 0b0000.

Burst size

Supported burst sizes are:

  • 8-bit.
  • 16-bit.
  • 32-bit.
  • 64-bit.
Burst type

ARBURST and AWBURST signals are always 0b01.

Because only bursts of one transfer are supported, burst type has no meaning in this context.

Atomic accesses

AXI-AP supports normal accesses only.

ARLOCK and AWLOCK signals are always 0b00.

Unaligned accesses
Unaligned accesses are not supported. Depending on the size of the transfers, addresses must be aligned.
  • For 16-bit halfword transfers, addresses are half-word aligned:

    • Base address 0x01 is aligned and AxADDR[7:0] = 0x00.
    • Base address 0x02 is retained and AxADDR[7:0] = 0x02.
  • For 32-bit word transfers, addresses are word aligned:

    • Base address 0x01-0x03 is aligned and AxADDR[7:0] = 0x00.
    • Base address 0x04 is retained and AxADDR[7:0] = 0x04.
  • For 64-bit doubleword transfers, addresses are double-word aligned:

    • Base address 0x04 is aligned and AxADDR[7:0] = 0x00.
    • Base address 0x08 is retained and AxADDR[7:0] = 0x08.
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