9 Supported Test Patterns/Modes Register, STPMR

The Supported Test Patterns/Modes Register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or TCD.

The STPMR register characteristics are:

Attributes
Offset

0x0200

Type

Read-only

Reset

0x0003000F

Width

32

The following figure shows the bit assignments.

Figure 9-450 STPMR register bit assignments
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The following table shows the bit assignments.

Table 9-465 STPMR register bit assignments

Bits Reset value Name Function
[31:18] 0b00000000000000 RAZ/WI

Read-As-Zero, Writes Ignored.

[17] 0b1 PCONTEN

Continuous Pattern Mode. Returns 1 indicating that continuous pattern mode is supported.

[16] 0b1 PTIMEEN

Timed Pattern Mode. Returns 1 indicating that timed pattern mode is supported.

[15:4] 0b000000000000 RAZ/WI

Read-As-Zero, Writes Ignored.

[3] 0b1 PATF0

FF/00 Pattern. Returns 1 indicating that the FF/00 pattern is supported over the trace port.

[2] 0b1 PATA5

AA/55 Pattern. Returns 1 indicating that the AA/55 pattern is supported over the trace port.

[1] 0b1 PATW0

Walking 0 Pattern. Returns 1 indicating that the walking 0s pattern is supported over the trace port

[0] 0b1 PATW1

Walking 1s Pattern. Returns 1 indicating that the walking 1s pattern is supported over the trace port.

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