4 Scatter list

The CATU uses a scatter list in memory to find the addresses of pages of memory to use for trace storage.

All the physical memory pages that are made available for trace data storage are 4KB. Each entry in the scatter list points to one of these 4KB pages.

The scatter list comprises a series of 4KB address regions, each region split into 2 x 2KB subpages. The base address of the scatter list is defined in the Scatter List Address High register, SLADDRHI and Scatter List Address Low register, SLADDRLO. At reset, the INADDRHI and INADDRLO registers contain a VA reference to the physical address that is defined in the SLADDRHI and SLADDRLO registers.

Each bottom 2KB subpage holds up to 256 64-bit physical addresses, each one pointing to a 4KB trace storage page in physical memory. Each top 2KB subpage holds only two addresses - the address of the next linked list and the address of the previous linked list. The address of the next linked list is the last entry in a 4KB list of pages, and the address of the previous linked list is the last-but-one entry. The total VA space that is covered by any 4KB scatter list is:

256 entries x 4KB pages = 1MB.

Scatter list address format

Each entry in the bottom 2KB subpage link list is made up as follows:

Figure 4-23 Structure of addresses that are used in VA → PA translation
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The addresses are used as follows:

  1. The top [VA_ADDR_MAX:20] bits of the virtual address are used to locate the required 4KB list of 4KB page physical addresses.
  2. Bits[19:12] of the VA are used as an index into the selected 4KB list to locate the 4KB page physical address.
  3. The page physical address is extracted from the list and bits[11:1] of the PA are replaced with the same bits from the VA.
  4. Bit[0] of the PA is used to indicate whether this page address is valid.

Note:

You must program the valid bit, bit[0], in the PAs for all addresses, including the addresses of the previous and next link lists that are contained in each of the top 2KB subpages. If a scatter list walk reads in a scatter list entry that does not have the valid bit set, then it is assumed that the top address page has been reached.

The following figure shows the overall structure of the scatter list.

Figure 4-24 Scatter list structure
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.