9 Register summary

The following table shows the registers in offset order from the base memory address.

Note:

A reset value containing one or more '-' means that this register contains UNKNOWN or IMPLEMENTATION-DEFINED values. See the relevant register description for more information.

Locations that are not listed in the table are Reserved.

Table 9-459 css600_tpiu - APB4_Slave_0 register summary

Offset

Name

Type

Reset

Width

Description

0x0000

SSPSR

RO

0x--------

32

Supported Port Size Register, SSPSR

0x0004

CSPSR

RW

0x00000001

32

Current Port Size Register, CSPSR

0x0100

STMR

RO

0x0000011F

32

Supported Trigger Modes Register, STMR

0x0104

TCVR

RW

0x00000000

32

Trigger Counter Value Register, TCVR

0x0108

TCMR

RW

0x00000000

32

Trigger Counter Multiplier Register, TCMR

0x0200

STPMR

RO

0x0003000F

32

Supported Test Patterns/Modes Register, STPMR

0x0204

CTPMR

RW

0x00000000

32

Current Test Patterns/Modes Register, CTPMR

0x0208

TPRCR

RW

0x00000000

32

Test Pattern Repeat Counter Register, TPRCR

0x0300

FFSR

RO

0x--------

32

Formatter and Flush Status Register, FFSR

0x0304

FFCR

RW

0x00001000

32

Formatter and Flush Control Register, FFCR

0x0308

FSCR

RW

0x00000040

32

Formatter Synchronization Count Register, FSCR

0x0400

EXTCTLIN

RO

0x--------

32

External Control Port In Register, EXTCTLIN

0x0404

EXTCTLOUT

RW

0x00000000

32

External Control Port Out Register, EXTCTLOUT

0x0EE8

ITTRFLIN

RO

0x00000000

32

Integration Test Trigger In and Flush In Register, ITTRFLIN

0x0EEC

ITATBDATA0

RO

0x00000000

32

Integration Test ATB Data Register 0, ITATBDATA0

0x0EF0

ITATBCTR2

WO

0x00000000

32

Integration Test ATB Control Register 2, ITATBCTR2

0x0EF4

ITATBCTR1

RO

0x00000000

32

Integration Test ATB Control Register 1, ITATBCTR1

0x0EF8

ITATBCTR0

RO

0x00000000

32

Integration Test ATB Control Register 0, ITATBCTR0

0x0EFC

ITOUTCTR

WO

0x00000000

32

Integration Test Output Control Register, ITOUTCTR

0x0F00

ITCTRL

RW

0x00000000

32

Integration Mode Control Register, ITCTRL

0x0FA0

CLAIMSET

RW

0x0000000F

32

Claim Tag Set Register, CLAIMSET

0x0FA4

CLAIMCLR

RW

0x00000000

32

Claim Tag Clear Register, CLAIMCLR

0x0FB8

AUTHSTATUS

RO

0x00000000

32

Authentication Status Register, AUTHSTATUS

0x0FBC

DEVARCH

RO

0x00000000

32

Device Architecture Register, DEVARCH

0x0FC8

DEVID

RO

0x00000020

32

Device Configuration Register, DEVID

0x0FCC

DEVTYPE

RO

0x00000011

32

Device Type Identifier Register, DEVTYPE

0x0FD0

PIDR4

RO

0x00000004

32

Peripheral Identification Register 4, PIDR4

0x0FD4

PIDR5

RO

0x00000000

32

Peripheral Identification Register 5, PIDR5

0x0FD8

PIDR6

RO

0x00000000

32

Peripheral Identification Register 6, PIDR6

0x0FDC

PIDR7

RO

0x00000000

32

Peripheral Identification Register 7, PIDR7

0x0FE0

PIDR0

RO

0x000000E7

32

Peripheral Identification Register 0, PIDR0

0x0FE4

PIDR1

RO

0x000000B9

32

Peripheral Identification Register 1, PIDR1

0x0FE8

PIDR2

RO

0x0000000B

32

Peripheral Identification Register 2, PIDR2

0x0FEC

PIDR3

RO

0x00000000

32

Peripheral Identification Register 3, PIDR3

0x0FF0

CIDR0

RO

0x0000000D

32

Component Identification Register 0, CIDR0

0x0FF4

CIDR1

RO

0x00000090

32

Component Identification Register 1, CIDR1

0x0FF8

CIDR2

RO

0x00000005

32

Component Identification Register 2, CIDR2

0x0FFC

CIDR3

RO

0x000000B1

32

Component Identification Register 3, CIDR3

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