|Home > Programmers model > css600_dp introduction > Register descriptions > Data Link Control Register, DLCR|
The DLCR controls the operating mode of the Data link. Access to this register is DATA LINK DEFINED. For JTAG-DP, this register is Reserved RES0. For SW-DP, the register programmer model is as shown in the following table.
The DLCR register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-8 DLCR register bit assignments
Turnaround tristate period.