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Arm® CoreSight™ System-on-Chip SoC-600 Technical Reference ManualRevision r3p0
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9 Data Link Control Register, DLCR

The DLCR controls the operating mode of the Data link. Access to this register is DATA LINK DEFINED. For JTAG-DP, this register is Reserved RES0. For SW-DP, the register programmer model is as shown in the following table.

The DLCR register characteristics are:

Attributes
Offset

0x0004
Type

Read-write
Reset

0x00000040
Width

32

The following figure shows the bit assignments.

Figure 9-7 DLCR register bit assignments
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The following table shows the bit assignments.

Table 9-8 DLCR register bit assignments

Bits Reset value Name Function
[9:8] 0b00 TURNROUND

Turnaround tristate period.

0x0

1 data period.
0x1

2 data periods.
0x2

3 data periods.
0x3

4 data periods.
[6] 0b1 RES1

Reserved, RES1.
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