9 Status register, STATUS

This register is the status register for the CATU, and the status of any AXI or VA address errors.

The STATUS register characteristics are:

Attributes
Offset

0x0100

Type

Read-only

Reset

0x00000100

Width

32

The following figure shows the bit assignments.

Figure 9-491 STATUS register bit assignments
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The following table shows the bit assignments.

Table 9-507 STATUS register bit assignments

Bits Reset value Name Function
[31:9] 0x0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[8] 0b1 READY

CATU ready. This bit indicates that the CATU is inactive and ready for programming, that is there are no ongoing operations. It is set when all of the following are true: AXI interfaces are not busy and the response for final AXI Master write has been received, that is there are no outstanding AXI transactions, and, there are no ongoing translations or translation requests.

[7:5] 0b000 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[4] 0b0 AXIERR

AXI error. This bit indicates that an error has been detected on the AXI interface. It is set when an error response is received or an unauthenticated transfer is attempted.

[3:1] 0b000 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[0] 0b0 ADDRERR

Virtual Address error. This bit indicates an error in the incoming VAs. It is set when the VA is less than the address that is defined in the Input Address Low and Input Address High registers, or the VA is larger than sum of the buffer size and the address that is defined in the Input Address Low and Input Address High registers. The buffer size = 4KB * <number of page address entries in the scatter list>.

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