9 Device Configuration Register, DEVID

This register is IMPLEMENTATION DEFINED for each Part Number and Designer. The register indicates the capabilities of the component.

The DEVID register characteristics are:

Attributes
Offset

0x0FC8

Type

Read-only

Reset

0x01040100

Width

32

The following figure shows the bit assignments.

Figure 9-575 DEVID register bit assignments
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The following table shows the bit assignments.

Table 9-594 DEVID register bit assignments

Bits Reset value Name Function
[31:25] 0b0000000 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[24] 0b1 INOUT

Indicates channel inputs are also masked by the CTIGATE register. Always 1.

[23:20] 0b0000 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[19:16] 0b0100 NUM_CH

The number of channels. Always 4.

[15:8] 0b00000001 NUM_TRIG

Indicates the maximum number of triggers - the maximum of the two parameters, NUM_EVENT_SLAVESand NUM_EVENT_MASTERS.

[7:5] 0b000 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[4:0] 0b00000 EXT_MUX_NUM

Indicates the value of the EXT_MUX_NUMparameter, which determines if there is any external multiplexing on the trigger inputs and outputs. 0 indicates no multiplexing.

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