2 APB Access Port

The css600_apbap module is a Memory Access Port (MEM-AP). The css600_apbap is an APB4 slave component that provides access to another APB4 memory system.

Use the css600_apbap to provide access to an APB4 memory space, for example:

  • A subsystem of CoreSight™ components that includes Arm® Cortex®-A or Cortex-R processors.
  • A subsystem of CoreSight components.
  • Any other APB4 memory system.

The APB Access Port allows visibility into another memory system from the debug APB infrastructure. Access Ports and related infrastructure can be cascaded in a CoreSight system to any depth. This process allows any memory system to contain a window into another memory system with a maximum memory footprint of 8KB in the source memory system.

The APB-AP provides an AMBA APB4 slave interface for programming and an AMBA APB4 master interface for accessing the target memory system. The programmers model contains the details of the registers for accessing the features of the APB4 master interface.

The APB-AP provides the following features:

  • Error response.
  • Stalling accesses.
  • Little endian only.
  • Single clock domain.
  • 32 bits data access only.
  • Auto-incrementing TAR.
  • An APB4 slave interface.
  • An APB4 master interface.
  • An authentication interface.
  • CoreSight Component base pointer register.
  • A Q-Channel LPI for high-level clock management.

The APB-AP does not support subword write transfers.


If the DP issues an abort over the Debug APB interface, the APB-AP completes the transaction on its Debug APB slave interface immediately. The DAP transfer abort does not cancel the ongoing APB transfer on the APB master interface.

The following figure shows the external connections on the APB Access Port.

Figure 2-2 css600_apbap logical connections
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