8 Cortex®‑A8 PIL debug memory map

The debug components in the Cortex®‑A8 PIL share memory space with the processor system.

paddrdbg[31] is inverted and mapped to paddrdbg[17] inside the PIL. The following tables show the locations of the Cortex‑A8 PIL CoreSight™ components.

See the Arm® CoreSight™ Architecture Specification v3.0 for information on the CoreSight ID scheme.

Table 8-4 Cortex‑A8 PIL debug memory map

APB address range Components Comments
0x00000000-0x00000FFF ROM table Start of external view of debug memory space
0x00010000-0x00010FFF Processor debug components A single 4KB block is used in the Cortex‑A8 processor
0x00018000-0x00018FFF CTI One CTI is present inside the processor
0x0001C000-0x0001CFFF ETM One optional ETM is present inside the processor
0x00020000-0x00020FFF Internal view of ROM table Start of internal debug view of debug memory space
0x00030000-0x00030FFF Processor debug components Location for self hosted debug access to processor debug components
0x0003C000-0x0003CFFF ETM Internal view
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