2 AHB Access Port

The css600_ahbap module is a Memory Access Port (MEM-AP). The css600_ahbap is an APB4 slave component that provides access to an AHB5 memory system.

Use the css600_ahbap to provide access to an AHB5 memory space, for example:

  • An Arm® Cortex®-M processor and subsystem.
  • Any other AHB5 memory system.

The AHB Access Port allows visibility into another memory system from the debug APB infrastructure. Access Ports and related infrastructure can be cascaded in a CoreSight™ system to any depth. This process allows any memory system to contain a window into another memory system with a maximum memory footprint of 8KB in the source memory system.

The AHB-AP provides an AMBA® APB4 slave interface for programming and an AMBA AHB5 master interface for accessing the target memory system. The programmers model contains the details of the registers for accessing the features of the AHB master interface.

The AHB-AP provides the following features:

  • Error response.
  • Stalling accesses.
  • Little endian only.
  • Single clock domain.
  • Auto-incrementing TAR.
  • An APB4 slave interface.
  • An AHB5 master interface.
  • An authentication interface.
  • 8 bits, 16 bits, or 32 bits data access.
  • CoreSight Component base pointer register.
  • Support for AHB5 TrustZone® signaling.
  • A Q-Channel LPI for high-level clock management.

The AHB-AP does not support:

  • Exclusive accesses.
  • Unaligned transfers.
  • BURST or SEQ transactions.

Note:

If the DP issues an abort over the Debug APB interface, the AHB-AP completes the transaction on its Debug APB slave interface immediately. The DAP transfer abort does not cancel the ongoing AHB transfer.

The following figure shows the external connections on the AHB Access Port.

Figure 2-3 css600_ahbap logical connections
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