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DISABLING is an emergency stop state that can be entered at any time by clearing CTL.TraceCaptEn.
DISABLING state differs from the STOPPING state in the following ways:
Exit from DISABLING state is not dependent on reads performed from the RRD register, in SWF1 and SWF2 modes, or the ATB Master interface accepting writes in HWF mode.
If the FIFO is full, then existing data is overwritten to enable the STOP sequence to complete. If a memory error occurs in DISABLING state, or if the STS.MemErr bit is already set and a hard stop occurs, more AXI writes are not performed. If this situation happens, the TMC discards the trace that is not output and directly moves from DISABLING to DISABLED state.
Arm recommends that the trace capture is stopped by programming an appropriate STOP event in the FFCR register. For example, trace capture can be stopped by setting the FFCR.StopOnFl bit, and then initiating a manual flush by setting the FFCR.FlushMan bit.
The emergency stop option is provided so that the TMC is programmer-compatible with the ETB that was delivered with SoC-400, where the only way to stop trace capture was by clearing CTL.TraceCaptEn bit. Use of the emergency stop is otherwise discouraged, especially in FIFO modes, where it can lead to loss of trace or even trace corruption.
In ETR and ETS configurations, transition from DISABLING to DISABLED state is delayed indefinitely if the AXI or AXI Stream interface is stalled indefinitely. In this case, you must clear the source of the stall, since it is not possible to abort a transfer when it has started.