9 Control Status Word register, CSW

The CSW register configures and controls accesses through the AHB master interface to the connected memory system.

The CSW register characteristics are:

Attributes
Offset

0x0D00

Type

Read-write

Reset

0x43-000-2

Width

32

The following figure shows the bit assignments.

Figure 9-54 CSW register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-57 CSW register bit assignments

Bits Reset value Name Function
[31] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[30] 0b1 HNONSEC

Drives hnonsec_m output pin. Together with authentication interface signals HNONSEC determines whether a secure access is allowed on the master interface as follows, access = dbgen && spiden || dbgen && HNONSEC.

[29:28] 0b00 RAZ/WI

Read-As-Zero, Writes Ignored.

[27:24] 0b0011 HPROT

Specifies the protection signal encoding to be output on hprot_m[3:0]. CSW.HPROT[3] also drives hprot_m[6] and hprot_m[4]. Reset to 0x3 (Non-Shareable, Non-Lookup, Non-Modifiable, Non-Bufferable, Privileged, Data).

[23] UNKNOWN SDeviceEn

Indicates the status of the spiden and spniden ports. It is set when either spiden or spniden is HIGH, and remains clear otherwise. If this bit is clear, Secure AHB transfers are not permitted. Non-secure memory accesses and internal register accesses that do not initiate memory accesses are permitted regardless of the status of this bit.

[22:18] 0b00000 RAZ/WI

Read-As-Zero, Writes Ignored.

[17] 0b0 ERRSTOP

Stop on error.

0

Memory access errors do not prevent future memory accesses.

1

Memory access errors prevent future memory accesses.

[16] 0b0 ERRNPASS

Errors that are not passed upstream.

0

Memory access errors that are passed upstream.

1

Memory access errors that are not passed upstream.

[15:12] 0b0000 Type

This field is reserved. Reads return 0x0 and writes are ignored.

[11:8] 0b0000 Mode

Specifies the mode of operation. All other values are reserved.

0x0

Normal download or upload mode.

[7] 0b0 TrInProg

Transfer in progress. This field indicates whether a transfer is in progress on the AHB master interface. If the master interface is busy, CSW.TrInProg is set in both logical APs.

[6] UNKNOWN DeviceEn

Indicates the status of dbgen and niden ports. The bit is set when either dbgen or niden is high, and is clear otherwise. If this bit is clear, no AHB transfers are carried out, that is, both secure and non-secure accesses are blocked).

[5:4] 0b00 AddrInc

Auto address increment mode on RW data access. Only increments if the current transaction completes without an error response and the transaction is not aborted.

0x0

Auto increment OFF.

0x1

Increment, single. Single transfer from corresponding byte lane.

0x2

Reserved.

0x3

Reserved.

[3] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[2:0] 0b010 Size

Size of the data access to perform.

0x0

8 bits.

0x1

16 bits.

0x2

32 bits.

0x3

Reserved.

0x4

Reserved.

0x5

Reserved.

0x6

Reserved.

0x7

Reserved.

Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.