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CoreSight™ SoC-600 Memory Access Ports (MEM-APs) implement Error Response Handling Version 1.
Error Response Handling V1 is defined in the Arm® Debug Interface Architecture Specification ADIv6.0. Support for this error handling mechanism is indicated in the CFG.ERR register field. The three register bits CSW.ERRNPASS, CSW.ERRSTOP, and TRR.ERR are used to define the behavior of this feature. See the relevant programmers model register descriptions for more information.
The MEM AP logs errors in Transfer Response Register by setting TRR.ERR bit to 1. When set, this bit remains set until software clears it by writing 1 to it. The following types of memory access errors are logged:
|Authentication failure||This error is due to an unauthenticated memory access attempt, such as:
|Stopped on error||This error is due to a memory access attempt when TRR.ERR=1 and CSW.ERRSTOP=1.|
|AHB/APB/AXI error||An error response that is received on the AP master interface indicating that the memory access failed.|
|Abort||Aborted memory transfers.|
|Master busy||This error happens if a memory access is attempted after an abort, but while the CSW.TrInProg bit is still set.|
|Invalid transaction||This error only applies to the AXI-AP when a memory access is attempted with an invalid combination of CSW.Cache and CSW.Domain fields.|
Internal register access errors are not logged in the TRR but are always passed on the APB slave interface. If a register write is attempted after an abort while the CSW.TrInProg bit is set, an error is generated.
The register bit CSW.ERRNPASS controls whether a memory access error is passed back to the requestor. The internal register access errors are always passed back on the APB slave interface regardless of the value of this bit.
The CSW.ERRNPASS bit has the following effect on behavior:
|0||Memory access errors are passed back on the APB slave interface.|
|1||Memory access errors are not passed back on the APB slave interface. In this case, a normal APB response is returned even for failed memory transactions.|
There are two exceptions to this rule. In both cases, the error is always passed on the APB slave interface, regardless of the status of the CSW.ERRNPASS bit. The exceptions are:
The APB read data for all transactions that generate an error is UNKNOWN.
If no previous memory access errors are logged, that is TRR.ERR=0, memory accesses are allowed, regardless of the state of CSW.ERRSTOP.
If a previous memory access error is still logged, that is TRR.ERR=1, the register field CSW.ERRSTOP controls whether to prevent memory accesses as follows:
The following table summarizes this MEM AP behavior for memory errors other than Abort and Master Busy.
Table 2-2 MEM-AP behavior for memory errors other than Abort and Master Busy
|TRR.ERR||CSW.ERRNPASS||CSW.ERRSTOP||New Memory Access||Slave Error||Error logged|
|0||0||x||Allowed if Authenticated, otherwise blocked.||Passed||Yes|
The twin logical APs implement error handling independently, and the errors that are received or generated on one do not affect the other.
Memory errors, other than Abort and Master-Busy, are maskable errors. That is, they can be masked from appearing on an APB slave interface by setting the CSW.ERRNPASS bit. It is possible for a single memory access to cause multiple error sources to generate errors at the same time. For example, a memory access can trigger a stop-on-error and an authentication failure.
If an error is masked, an error response is passed on the APB slave interface, even if CSW.ERRNPASS is 1, and if at least one of the sources of error is non-maskable (Abort or Master-Busy). If all the triggered error sources are maskable, the error is passed only if CSW.ERRNPASS is 0.
If the Authentication interface signals change while a memory transfer is in progress, the MEM AP still completes the ongoing transfer normally. The new Authentication interface values then take effect from the next transaction. If a memory access request is received while the MEM AP is in Q_STOPPED state, the authentication signal values are sampled only after entering Q_RUN state in the first cycle, and that value is used to determine whether to allow or block the pending APB transfer.