9 Supported Port Size Register, SSPSR

This register shows supported width configurations of the tracedata port. Each bit location represents a single port size that is supported, that is sizes 32 bits down to 1 bit, in bit locations [31:0]. If a bit is set, then that port size is supported. By default, the RTL is designed to support all port sizes. Port sizes, other than 1-bit, are configuration-dependent on the tie-off value of tp_maxdatasize. Bit[0] is always 1.

The SSPSR register characteristics are:

Attributes
Offset

0x0000

Type

Read-only

Reset

0x--------

Width

32

The following figure shows the bit assignments.

Figure 9-445 SSPSR register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-460 SSPSR register bit assignments

Bits Reset value Name Function
[31:0] IMPLEMENTATION_DEFINED SSPSR

Supported tracedata port sizes. Bit[0] is always 1.

Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.