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This register controls the value of the addrerr interrupt output in integration mode, that is when ITCTRL.IME is set. In normal mode this register behaves as RAZ/WI. In integration mode the value written to bit of this register is driven on the addrerr output pin.
The ITIRQ register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-508 ITIRQ register bit assignments
Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.
In Integration Test Mode the addrerr output is directly controlled by this bit.