9 Integration Test ATB Control 2 Register, ITATBCTR2

This register enables control of ATB slave outputs atready_s, afvalid_s, and syncreq_s in integration mode. In functional mode, this register behaves as RAZ/WI. In integration mode, the value that is written to any bit of this register is driven on the output pin that is controlled by that bit and the reads return 0x0.

The ITATBCTR2 register characteristics are:

Attributes
Offset

0x0EF0

Type

Write-only

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-298 ITATBCTR2 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-309 ITATBCTR2 register bit assignments

Bits Reset value Name Function
[31:3] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[2] 0b0 SYNCREQS

Controls the value of syncreq_s output in integration mode.

[1] 0b0 AFVALIDS

Controls the value of afvalid_s output in integration mode.

[0] 0b0 ATREADYS

Controls the value of atready_s output in integration mode.

Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.