9 Integration Test ATB Data Register 0, ITATBDATA0

This register indicates the value of the atdata_s input in integration mode. Only 5 bits are readable through this register, the MSB of each of the four data bytes and the LSB. Reads are allowed even in functional mode, but the register is disabled and does not get updated even if the inputs change. The reset value depends on the external source driving the inputs.

The ITATBDATA0 register characteristics are:

Attributes
Offset

0x0EEC

Type

Read-only

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-459 ITATBDATA0 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-474 ITATBDATA0 register bit assignments

Bits Reset value Name Function
[31:5] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[4] 0b0 ATDATA_31

Reads the value of atdata_s[31] during integration mode.

[3] 0b0 ATDATA_23

Reads the value of atdata_s[23] during integration mode.

[2] 0b0 ATDATA_15

Reads the value of atdata_s[15] during integration mode.

[1] 0b0 ATDATA_7

Reads the value of atdata_s[7] during integration mode.

[0] 0b0 ATDATA_0

Reads the value of atdata_s[0] during integration mode.

Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.