9 AXI Control Register, AXICTL

This register controls TMC accesses to system memory through the AXI interface. The TMC only performs data accesses, so the arprot_m[2] and awprot_m[2] outputs are LOW for all AXI transfers.

The AXICTL register characteristics are:

Attributes
Offset

0x0110

Type

Read-write

Reset

0x00000-0-

Width

32

The following figure shows the bit assignments.

Figure 9-377 AXICTL register bit assignments
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The following table shows the bit assignments.

Table 9-390 AXICTL register bit assignments

Bits Reset value Name Function
[31:20] 0b000000000000 RAZ/WI

Read-As-Zero, Writes Ignored.

[19:16] 0b0000 RCACHE

This field controls the AXI cache encoding for read transfers, that is, the value to be driven on the arcache_m[3:0] bus. Software must only program a valid AXI3 or AXI4 cache encoding value in this field, these are defined in the AMBA 4 AXI and ACE Protocol Specification.If software attempts to program an invalid value 0x0 is written to this field instead.

[15:12] 0b0000 RAZ/WI

Read-As-Zero, Writes Ignored.

[11:8] UNKNOWN WrBurstLen

Write Burst Length. This field indicates the maximum number of data transfers that can occur within each burst that is initiated by the TMC on the AXI interface. The write burst that is initiated on the AXI can be shorter than the programmed value in a case when the formatter has stopped due to a stop condition having occurred.

[7:6] 0b00 RAZ/WI

Read-As-Zero, Writes Ignored.

[5:2] 0b0000 WCACHE

This field controls the AXI cache encoding for write transfers, that is, the value to be driven on the awcache_m[3:0] bus. Software must only program a valid AXI3 or AXI4 cache encoding value in this field, which are defined in AMBA 4 AXI and ACE Protocol Specification. If software attempts to program an invalid value, 0x0 is written to this field instead.

[1] UNKNOWN ProtCtrlBit1

Secure Access (AXI4 definition). This bit controls the value that is driven on arprot_m[1] or awprot_m[1] on the AXI master interface when performing AXI transfers.

[0] UNKNOWN ProtCtrlBit0

Privileged Access (AXI4 definition). This bit controls the value that is driven on arprot_m[0] or awprot_m[0] on the AXI master interface when performing AXI transfers.

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