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Arm® CoreSight™ System-on-Chip SoC-600 Technical Reference ManualRevision r3p0
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9 Device Architecture Register, DEVARCH

Identifies the architect and architecture of a CoreSight component. The architect might differ from the designer of a component, for example Arm defines the architecture but another company designs and implements the component.

The DEVARCH register characteristics are:

Attributes
Offset

0x0FBC
Type

Read-only
Reset

0x47700A17
Width

32

The following figure shows the bit assignments.

Figure 9-70 DEVARCH register bit assignments
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The following table shows the bit assignments.

Table 9-73 DEVARCH register bit assignments

Bits Reset value Name Function
[31:21] 0b01000111011 ARCHITECT

Returns 0x23B, denoting Arm as architect of the component.
[20] 0b1 PRESENT

Returns 1, indicating that the DEVARCH register is present.
[19:16] 0b0000 REVISION

Architecture revision. Returns the revision of the architecture that the ARCHID field specifies.
[15:0] 0xA17 ARCHID

Architecture ID. Returns 0x0A17, identifying APv2 MEM-AP architecture v0.
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