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This register indicates the integration status of the flushin and trigin inputs in integration mode. Reads are allowed even in functional mode, but the register itself is disabled and does not get updated even if the inputs change. The reset value depends on the external source driving the inputs.
The ITTRFLIN register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-473 ITTRFLIN register bit assignments
Read-As-Zero, Writes Ignored.
In integration mode, this bit latches to 1 on a rising edge of the flushin input. It is cleared when this register is read, or when integration mode is disabled.
In integration mode, this bit latches to 1 on a rising edge of the trigin input. It is cleared when this register is read or when integration mode is disabled.