8 Cortex®‑A9 PIL debug memory map

The debug components in the Cortex®‑A9 PIL share memory space with the processor system.

The following table shows the locations of the Cortex‑A9 PIL CoreSight™ components.

Table 8-6 Cortex‑A9 PIL debug memory map

APB address range Components Comments
0x00000000-0x00000FFF ROM table Start of external view of debug memory space.
0x00010000-0x000101FF, or 0x00010000-0x000103FF, or 0x00010000-0x000107FF Processor 0 debug components

Depending on the multiprocessor configuration, the debug components occupy a memory space as follows:

Single processor13 bits, 8KB.
Two processors14 bits, 16KB.
Three or four processors15 bits, 32KB.
0x00018000-0x00018FFF CTI0 Always present.
0x00019000-0x00019FFF CTI1 Present if two or more processors are present.
0x0001A000-0x0001AFFF CTI1 Present if three or more processors are present.
0x0001B000-0x0001BFFF CTI3 Present if four processors are present.
0x0001C000-0x0001CFFF PTM0 Present if PTM is configured.
0x0001D000-0x0001DFFF PTM1 Present if PTM configured and processor 1 is present and no PTM sharing.
0x0001E000-0x0001EFFF PTM2 Present if PTM configured and processor 2 is present and no PTM sharing.
0x0001F000-0x0001FFFF PTM3 Present if PTM configured and processor 3 is present and no PTM sharing.
0x00020000-0x00020FFF Internal view of ROM table Start of internal debug view of debug memory space.
0x00030000-0x000301FF, or 0x00030000-0x000303FF, or 0x00030000-0x000307FF Processor debug components Location self hosted debug access to processor debug components. Same dependencies on configuration as external view.
0x0003F000-0x0003FFFF PTM3 Location of self-hosted access to PTM3.
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