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In ETR configuration, the AXI master interface replaces the memory interface that is used in ETB and ETF configurations.
The interface can be connected to an AXI interconnect for accessing system memory through a memory controller or can be connected to any other AXI slave in the system.
The AXI master interface supports up to 32 outstanding write transactions and zero outstanding reads. If an error response is returned at any time, the interface stops the operation until the debugger identifies and clears the error condition.
In ETR configuration, the memory size is programmable, rather than configurable. The
width of the RSZ register determines the maximum size of the trace memory. The
register is 31-bits wide, allowing a maximum value of
0x40000000, representing 4GB. The trace memory can be located anywhere in
the system address space with the start address aligned to a 4KB boundary. Some of
the lower bits of AXI address buses araddr_m and awaddr_m
are tied to 0 to ensure that all accesses are aligned to the AXI data width. The
number of bits to be tied to 0 is calculated as
log2(AXI_DATA_WIDTH/8). For example, when the
AXI data bus is 64-bits wide, the lower 3 bits of the address buses are tied to 0 to
ensure that only 64-bit aligned accesses are used.