4 Address validation

The input address registers define the lower boundary of the valid address range.

The input address registers are INADDRHI and INADDRLO.

If the VA is less than the address that is defined in the input address registers, then the CATU sets the status bit STATUS.ADDRERR. If the interrupt is enabled, the CATU also generates an interrupt to indicate an address error.

The scatter list walker iterates through the table until the correct translation is found or an invalid entry is hit. When the scatter list walker returns an entry with valid == 0, then the upper bound has been reached. In this case, if enabled, an interrupt is generated, the CATU sets the status bit STATUS.ADDRERR, and the out-of-range incoming transaction gets an error response.

The following figure shows the address validation.

Figure 4-25 Address validation
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