Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Arm® CoreSight™ System-on-Chip SoC-600 Technical Reference ManualRevision r3p0
Home > Programmers model > css600_dp introduction > Register descriptions > Debug Port Identification Register 1, DPIDR1

9 Debug Port Identification Register 1, DPIDR1

The DPIDR1 register is the extension of DPIDR and provides information about the Debug Port.

The DPIDR1 register characteristics are:

Attributes
Offset

0x0000
Type

Read-only
Reset

0x0000008C
Width

32

The following figure shows the bit assignments.

Figure 9-3 DPIDR1 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-4 DPIDR1 register bit assignments

Bits Reset value Name Function
[7] 0b1 ERRMODE

Error reporting mode support.

0

CTRLSTAT.ERRMODE not implemented.
1

CTRLSTAT.ERRMODE implemented.
[6:0] 0b0001100 ASIZE

Address size. This defines the size of the address in the SELECT register, and the BASEPTR0 register. Allowed values are 0x0C: 12-bit address, 0x14: 20-bit address, 0x20: 32-bit address. All other values are reserved.

This is an implementation-defined value that depends on the configuration of the component.
Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved. 
Home > Programmers model > css600_dp introduction > Register descriptions > Debug Port Identification Register 1, DPIDR1