9 Register summary

The following table shows the registers in offset order from the base memory address.

Note:

A reset value containing one or more '-' means that this register contains UNKNOWN or IMPLEMENTATION-DEFINED values. See the relevant register description for more information.

Locations that are not listed in the table are Reserved.

Table 9-528 css600_tsgen - APB4_Slave_0 register summary

Offset

Name

Type

Reset

Width

Description

0x0000

CNTCR

RW

0x00000000

32

Counter Control Register, CNTCR

0x0004

CNTSR

RO

0x00000000

32

Counter Status Register, CNTSR

0x0008

CNTCVL

RW

0x00000000

32

Current value of Counter[31:0], CNTCVL

0x000C

CNTCVU

RW

0x00000000

32

Current value of Counter[63:32], CNTCVU

0x0020

CNTFID0

RW

0x00000000

32

Base Frequency ID register, CNTFID0

0x0EF8

ITSTAT

RO

0x0000000-

32

Integration Test Status Register, ITSTAT

0x0F00

ITCTRL

RW

0x00000000

32

Integration Mode Control Register, ITCTRL

0x0FD0

PIDR4

RO

0x00000004

32

Peripheral Identification Register 4, PIDR4

0x0FD4

PIDR5

RO

0x00000000

32

Peripheral Identification Register 5, PIDR5

0x0FD8

PIDR6

RO

0x00000000

32

Peripheral Identification Register 6, PIDR6

0x0FDC

PIDR7

RO

0x00000000

32

Peripheral Identification Register 7, PIDR7

0x0FE0

PIDR0

RO

0x00000093

32

Peripheral Identification Register 0, PIDR0

0x0FE4

PIDR1

RO

0x000000B1

32

Peripheral Identification Register 1, PIDR1

0x0FE8

PIDR2

RO

0x0000000B

32

Peripheral Identification Register 2, PIDR2

0x0FEC

PIDR3

RO

0x00000000

32

Peripheral Identification Register 3, PIDR3

0x0FF0

CIDR0

RO

0x0000000D

32

Component Identification Register 0, CIDR0

0x0FF4

CIDR1

RO

0x000000F0

32

Component Identification Register 1, CIDR1

0x0FF8

CIDR2

RO

0x00000005

32

Component Identification Register 2, CIDR2

0x0FFC

CIDR3

RO

0x000000B1

32

Component Identification Register 3, CIDR3

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