4 Clock and reset

The TMC has a single clock input clk and an active LOW reset input reset_n.

reset_n resets all interfaces and control registers except some of the memory mapped control registers. See the appropriate Register summary for your chosen TMC configuration for details of registers that are not initialized on reset and must be programmed before enabling TMC trace capture.


When in ETR configuration, the TMC can be in a different power or reset domain from the AXI slave to which it is connected. An AMBA domain bridge is required to traverse the power or clock domain boundary in this case.
Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.