|Home > Programmers model > css600_tmc_etb introduction > Register descriptions > Formatter and Flush Status Register, FFSR|
This register indicates the status of the Formatter, and the status of Flush request.
The FFSR register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-303 FFSR register bit assignments
Read-As-Zero, Writes Ignored.
Formatter Stopped. This bit behaves the same way as STS.FtEmpty. It is cleared to 0 when leaving the Disabled state and retains its value when entering the Disabled state. The FFCR.FtStopped bit is deprecated and is present in this register to support backwards-compatibility with earlier versions of the ETB.
Flush In Progress. This bit indicates whether the TMC is currently processing a flush request. In the ETB and ETR configurations, the flush initiation is controlled by the flush control bits in the FFCR register. This bit is cleared to 0 when leaving the Disabled state and retains its value when entering the Disabled state. When in Disabled state, this bit is not updated.