4 Reads from TMC registers

You can only read from TMC registers under specific conditions.

The following table shows the conditions under which read accesses from TMC registers return valid values. Reads at other times return UNKNOWN values. An x indicates that any value is permitted.

Read accesses to TMC registers
Register Name Offset CTL.TraceCaptEn STS.TMCReady MODE ITCTRL Remarks
RSZ RAM Size register 0x004 x x x x
STS.MemErr Status Register 0x00C x x x 0
STS.Empty Status Register 0x00C 1 x x 0
STS.FtEmpty Status Register 0x00C x x x 0
STS.TMCReady Status Register 0x00C x x x 0
STS.Triggered Status Register 0x00C 1 x CB 0
0 x x 0 Value of this bit when trace capture stops is held.
STS.Full Status Register 0x00C x x x 0 Value of this bit when trace capture stops is held.
RRD RAM Read Data Register 0x010 0 1 x 0
1 x SWF1 0 If trace memory is empty, the data that is returned is 0xFFFFFFFF.
1 1 CB 0
RRP RAM Read Pointer Register 0x014 1 x SWF1, SWF2 0
1 1 CB 0
0 1 x 0
RWP RAM Write Pointer Register 0x018 1 x SWF1, SWF2 0
1 1 CB 0
0 1 x 0
TRG Trigger Counter Register 0x01C 1 x CB 0 The trigger counter is active only in Circular buffer mode.
0 1 x 0
CTL Control Register 0x020 x X x 0
RWD RAM Write Data Register 0x024 Write-only
MODE Mode Register 0x028 1 x x 0
LBUFLEVEL Latched Buffer Fill Level 0x02C 1 x x 0
0 1 x 0 Value of this register when trace capture stops is held.
CBUFLEVEL Current Buffer Fill Level 0x030 1 x x 0
0 1 x x Value of this register when trace capture stops is held.
BUFWM Buffer Level Water Mark 0x034 x x x x Programmed registers can be read at any time. The return value is the value that was programmed.
RRPHI RAM Read Pointer High Register 0x038 1 x SWF1, SWF2 0 -
1 1 CB 0 -
0 1 x 0 -
RWPHI RAM Write Pointer High Register 0x03C 1 0 SWF1, SWF2 0 -
1 1 CB 0 -
0 1 x 0 -
AXICTL AXI Control Register 0x110 x x x x -
DBALO Data Buffer Address Low Register 0x118 x x x x -
DBAHI Data Buffer Address High Register 0x11C x x x x -
RURP RAM Update Read Pointer Register 0x120 Write-only
FFSR Formatter and Flush Status Register 0x300 x x x 0 -
FFCR Formatter and Flush Control Register 0x304 x x x 0 -
PSCR Periodic Synchronization Counter Register 0x308 x x x 0 -
ITATBMDATA0 Integration Test ATB Master Data 0 Register 0xED0 Write-only
ITATBMCTR2 Integration Test ATB Master Interface Control 2 Register 0xED4 x x x 1 -
ITATBMCTR1 Integration Test ATB Master Interface Control 1 Register 0xED8 x x x 1 -
ITATBMCTR0 Integration Test ATB Master Interface Control 0 Register 0xEDC Write-only
ITEVTINTR Integration Test Event & Interrupt Status Register 0xEE0 Write-only
ITTRFLIN Integration Test Trigger In and Flush In Register 0xEE8 x x x 1 -
ITATBDATA0 Integration Test ATB Data Register 0 0xEEC x x x 1 -
ITATBCTR2 Integration Test ATB Control 2 Register 0xEF0 Write-only
ITATBCTR1 Integration Test ATB Control 1 Register 0xEF4 x x x 1 -
ITATBCTR0 Integration Test ATB Control 0 Register 0xEF8 x x x 1 -
ITCTRL Integration Mode Control Register 0xF00 x x x x -
CLAIMSET Claim Tag Set Register 0xFA0 x x x x -
CLAIMCLR Claim Tag Clear Register 0xFA4 x x x x -
AUTHSTATUS Authentication Status Register 0xFB8 x x x x -
DEVARCH Device Architecture Register 0xFBC x x x x -
DEVID Device Configuration Register 0xFC8 x x x x -
DEVTYPE Device Type Identifier Register 0xFCC x x x x -
PIDR4-7 Peripheral ID Registers 4-7 0xFD0-0xFDC x x x x -
PIDR0-3 Peripheral ID Registers 0-3 0xFE0-0xFEC x x x x -
CIDR0-3 Component ID Registers 0-3 0xFF0-0xFFC x x x x -
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