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Home > Programmers model > css600_tmc_etf introduction > Register summary |
The following table shows the registers in offset order from the base memory address.
A reset value containing one or more '-' means that this register contains UNKNOWN or IMPLEMENTATION-DEFINED values. See the relevant register description for more information.
Locations that are not listed in the table are Reserved.
Table 9-331 css600_tmc_etf - APB4_Slave_0 register summary
Offset |
Name |
Type |
Reset |
Width |
Description |
---|---|---|---|---|---|
|
RSZ |
RW |
|
32 |
|
|
STS |
RW |
|
32 |
|
|
RRD |
RO |
|
32 |
|
|
RRP |
RW |
|
32 |
|
|
RWP |
RW |
|
32 |
|
|
TRG |
RW |
|
32 |
|
|
CTL |
RW |
|
32 |
|
|
RWD |
WO |
|
32 |
|
|
MODE |
RW |
|
32 |
|
|
LBUFLEVEL |
RO |
|
32 |
|
|
CBUFLEVEL |
RO |
|
32 |
|
|
BUFWM |
RW |
|
32 |
|
|
FFSR |
RO |
|
32 |
|
|
FFCR |
RW |
|
32 |
|
|
PSCR |
RW |
|
32 |
|
|
ITATBMDATA0 |
WO |
|
32 |
|
|
ITATBMCTR2 |
RO |
|
32 |
9 Integration Test ATB Master Control 2 register, ITATBMCTR2 |
|
ITATBMCTR1 |
WO |
|
32 |
9 Integration Test ATB Master Control 1 register, ITATBMCTR1 |
|
ITEVTINTR |
WO |
|
32 |
9 Integration Test Event and Interrupt Control Register, ITEVTINTR |
|
ITTRFLIN |
RO |
|
32 |
9 Integration Test Trigger In and Flush In register, ITTRFLIN |
|
ITATBDATA0 |
RO |
|
32 |
|
|
ITATBCTR2 |
WO |
|
32 |
|
|
ITATBCTR1 |
RO |
|
32 |
|
|
ITATBCTR0 |
RO |
|
32 |
|
|
ITCTRL |
RW |
|
32 |
|
|
CLAIMSET |
RW |
|
32 |
|
|
CLAIMCLR |
RW |
|
32 |
|
|
AUTHSTATUS |
RO |
|
32 |
|
|
DEVID1 |
RO |
|
32 |
|
|
DEVID |
RO |
|
32 |
|
|
DEVTYPE |
RO |
|
32 |
|
|
PIDR4 |
RO |
|
32 |
|
|
PIDR5 |
RO |
|
32 |
|
|
PIDR6 |
RO |
|
32 |
|
|
PIDR7 |
RO |
|
32 |
|
|
PIDR0 |
RO |
|
32 |
|
|
PIDR1 |
RO |
|
32 |
|
|
PIDR2 |
RO |
|
32 |
|
|
PIDR3 |
RO |
|
32 |
|
|
CIDR0 |
RO |
|
32 |
|
|
CIDR1 |
RO |
|
32 |
|
|
CIDR2 |
RO |
|
32 |
|
|
CIDR3 |
RO |
|
32 |