8 Cortex®‑M0 PIL debug memory map

The debug components in the Cortex®‑M0 PIL share memory space with the processor system.

You must build your system level interconnect so that the PIL Debug Component Slave (DCS) AHB-Lite port is accessed for the address ranges of the PIL components.

The following table shows the locations of the Cortex‑M0 PIL CoreSight™ components.

Table 8-12 Cortex‑M0 PIL debug memory map

Address range Components
0xF0000000-0xF0000FFF PIL primary ROM table.
0xF0001000-0xF0001FFF CTI.
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