9 Formatter and Flush Control Register, FFCR

This register allows user control of the stop, trigger, and flush events.

The FFCR register characteristics are:

Attributes
Offset

0x0304

Type

Read-write

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-333 FFCR register bit assignments
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The following table shows the bit assignments.

Table 9-345 FFCR register bit assignments

Bits Reset value Name Function
[31:16] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[15] 0b0 EmbedFlush

Embed Flush ID (flush completion packet). Enables insertion of Flush ID 0x7B with a single byte of data payload = 0x00 in the output trace, immediately after the last flush data byte, when a flush completes on the ATB slave interface. This bit is effective only in Normal formatting modes. In Bypass mode, the Flush ID insertion remains disabled and this bit is ignored.

0

Disable Flush ID insertion.

1

Enable Flush ID insertion.

[14] 0b0 DrainBuffer

Drain Buffer. This bit is used to enable draining of the trace data through the ATB master interface after the formatter has stopped. It is useful in CB mode to capture trace data into trace memory and then to drain the captured trace through the ATB master interface. Writing a 1 to this bit when in Stopped state starts the drain of the contents of trace buffer. This bit always reads as 0. The STS.TMCReady bit goes LOW while the drain is in progress. This bit is functional only when the TMC is in CB mode and formatting is enabled, that is, FFCR.EnFt=1. Setting this bit when the TMC is in any other mode, or when not in Stopped state, results in UNPREDICTABLE behavior. When trace capture is complete in CB mode, all of the captured trace must be retrieved from the trace memory, either by reading all trace data out through RRD reads, or draining all trace data by setting the FFCR.DrainBuffer bit. Setting this bit after some of the captured trace has been read out through RRD results in UNPREDICTABLE behavior.

[13] 0b0 StopOnTrigEvt

Stop On Trigger Event. If this bit is set, the formatter is stopped when a Trigger Event has been observed. This bit must be used only in CB mode because in FIFO modes, the TMC is a trace link rather than a trace sink and trigger events are related to trace sink functionality. If trace capture is enabled in SWF1, SWF2, or HWF mode with this bit set, it results in UNPREDICTABLE behavior.

[12] 0b0 StopOnFl

Stop On Flush. If this bit is set, the formatter is stopped on completion of a flush operation. The initiation of a flush operation is controlled by programming the register bits FFCR.FlushMan, FFCR.FOnTrigEvt, and FFCR.FOnFlIn. When a flush-initiation condition occurs, afvalid_s is asserted, and when the flush completion is received, that is, afready_s=1, trace capture is stopped. Any remaining data in the formatter is appended with a post-amble and written to trace memory. The flush operation is then complete. When the TMC is configured as an ETF, if a flush is initiated by the ATB Master interface, its completion does not lead to a formatter stop regardless of the value that is programmed in this bit.

[11] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[10] 0b0 TrigOnFl

Indicate on trace stream the completion of flush. If this bit is set, a trigger is indicated on the trace stream when afready_s is received for a flush in progress. If this bit is clear, no triggers are embedded in the trace stream on flush completion. If Trigger Insertion is disabled, that is, FFCR.EnTI=0, then trigger indication on the trace stream is blocked regardless of the value that is programmed in this bit. When the TMC is configured as ETF, if a flush is initiated by the ATB Master interface, its completion does not lead to a trigger indication on the trace stream regardless of the value that is programmed in this bit.

[9] 0b0 TrigOnTrigEvt

Indicate on trace stream the occurrence of a Trigger Event. If this bit is set, a trigger is indicated on the output trace stream when a Trigger Event occurs. If Trigger Insertion is disabled, that is, FFCR.EnTI=0, then trigger indication on the trace stream is blocked regardless of the value that is programmed in this bit. This bit must be used only in CB mode because in FIFO modes, the TMC is a trace link rather than a trace sink and trigger events are related to trace sink functionality. If trace capture is enabled in SWF1, SWF2, or HWF mode with this bit set, it results in UNPREDICTABLE behavior.

[8] 0b0 TrigOnTrigIn

Indicate on trace stream the occurrence of a rising edge on trigin. If this bit is set, a trigger is indicated on the trace stream when a rising edge is detected on the trigin input. If Trigger Insertion is disabled, that is, FFCR.EnTI=0, then trigger indication on the trace stream is blocked regardless of the value that is programmed in this bit.

[7] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[6] 0b0 FlushMan

Manually generate a flush of the system. Writing 1 to this bit causes a flush to be generated. This bit is cleared automatically when, in formatter bypass mode, afready_s was sampled high, or, in normal formatting mode, afready_s was sampled high and all flush data was output to the trace memory. If CTL.TraceCaptEn=0, writes to this bit are ignored.

[5] 0b0 FOnTrigEvt

Flush on Trigger Event. Setting this bit generates a flush when a Trigger Event occurs. If FFCR.StopOnTrigEvt is set, this bit is ignored. This bit must be used only in CB mode because in FIFO modes, the TMC is a trace link rather than a trace sink and trigger events are related to trace sink functionality. If trace capture is enabled in SWF1, SWF2, or HWF mode with this bit set, it results in UNPREDICTABLE behavior.

[4] 0b0 FOnFlIn

Setting this bit enables the detection of transitions on the flushin input by the TMC. If this bit is set and the formatter has not already stopped, a rising edge on flushin initiates a flush request.

[3:2] 0b00 RAZ/WI

Read-As-Zero, Writes Ignored.

[1] 0b0 EnTI

Enable Trigger Insertion. Setting this bit enables the insertion of triggers in the formatted trace stream. A trigger is indicated by inserting one byte of data 0x00 with atid_s=0x7D in the trace stream. Trigger indication on the trace stream is also controlled by the register bits FFCR.TrigOnFl, FFCR.TrigOnTrigEvt, and FFCR.TrigOnTrigIn. This bit can only be changed when the TMC is in Disabled state. If FFCR.EnTI bit is set when FFCR.EnFt is 0, it results in formatting being enabled.

[0] 0b0 EnFt

Enable Formatter. If this bit is set, formatting is enabled. This bit takes effect when not in Disabled state, and is ignored in Disabled state. If this bit is clear, formatting is disabled. In this case, the incoming trace data is assumed to be from a single trace source. If multiple trace IDs are received by the TMC when trace capture is enabled and the formatter is disabled, it results in interleaving of trace data. Disabling of formatting is deprecated, and is supported in the TMC for backwards-compatibility with earlier versions of the ETB. Therefore, disabling of formatting is supported only in CB mode. Features in the TMC such as the FIFO modes and the FFCR.DrainBuffer bit that are not part of the earlier versions of the ETB do not support disabling of formatting. This bit can only be changed when TMC is in Disabled state. If FFCR.EnTI bit is set when FFCR.EnFt is 0, it results in formatting being enabled. If the TMC is enabled in a mode other than Circular Buffer mode with formatting disabled, it results in formatting being enabled.

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