9 Formatter and Flush Control Register, FFCR

The FFCR controls the generation of stop, trigger, and flush events in the TPIU. It also controls insertion of flush completion packets in the output trace.

The FFCR register characteristics are:

Attributes
Offset

0x0304

Type

Read-write

Reset

0x00001000

Width

32

The following figure shows the bit assignments.

Figure 9-454 FFCR register bit assignments
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The following table shows the bit assignments.

Table 9-469 FFCR register bit assignments

Bits Reset value Name Function
[31:16] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[15] 0b0 EmbedFlush

Embed flush completion packet, Flush ID. Enables insertion of Flush ID 0x7B with a single byte of data payload = 0x00 in the output trace, after the last flush data byte, when a flush completes on the ATB slave interface. This bit is effective only in Normal and Continuous formatter modes. In Bypass mode, the Flush ID insertion remains disabled and this bit is ignored.

0

Disable Flush ID insertion

1

Enable Flush ID insertion

[14] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[13] 0b0 StopTrig

Stop on Trigger Event. Stops the formatter after a trigger event is observed.

0

Disable stopping the formatter after a trigger event is observed.

1

Enable stopping the formatter after a trigger event is observed.

[12] 0b1 StopFl

Stop on Flush Completion. Forces the FIFO to drain off any partially completed packets after a flush completion and stops the formatter.

0

Disable stopping the formatter when afready_s is received.

1

Enable stopping the formatter when afready_s is received.

[11] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[10] 0b0 TrigFl

Trigger on Flush Completion.

0

Disable trigger indication on flush completion, that is, when afready_s is high.

1

Enable trigger indication on flush completion.

[9] 0b0 TrigEvt

Trigger on Trigger Event. Indicates a trigger when the trigger counter reaches 0 while downcounting.

0

Disable trigger indication on trigger event.

1

Enable trigger indication on trigger event.

[8] 0b0 TrigIn

Trigger on trigin.

0

Disable trigger indication when trigin is asserted.

1

Enable trigger indication when trigin is asserted.

[7] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[6] 0b0 FOnMan

Flush Manual. Writing 1 to this bit generates a flush request on afvalid_s pin, writing 0 has no effect. It is automatically cleared when the generated flush request completes and afready_s is received by the TPIU. Reading this bit returns its current value.

[5] 0b0 FOnTrig

Flush on Trigger Event. Initiates a flush request when a trigger event occurs. A trigger event occurs when the trigger counter reaches 0 while downcounting, or, if the TCVR is 0x0 and trigin goes HIGH.

0

Disable generation of flush when a trigger event occurs.

1

Enable generation of flush when a trigger event occurs.

[4] 0b0 FOnFlIn

Flush on flushin.

0

Disable generation of flush using flushin input.

1

Enable generation of flush using flushin input.

[3:2] 0b00 RAZ/WI

Read-As-Zero, Writes Ignored.

[1] 0b0 EnFCont

Enable Continuous Formatting Mode. The trigger packets are embedded in the trace stream. This bit can only be changed when FFSR.FtStopped is HIGH.

[0] 0b0 EnFTC

Enable Formatter. The trigger packets are not embedded in the trace stream and the trace disable cycles and triggers are indicated by tracectl pin where present. This bit can only be changed when FFSR.FtStopped is HIGH.

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