Arm CoreSight System-on-Chip SoC-600 Technical Reference Manual : 9 Debug Base Address register, BASE

9 Debug Base Address register, BASE

Provides an initial system address for the first component in the system. Typically, the system address is the address of a top-level

The BASE register characteristics are:

Attributes

Offset	`0x0DF8`
Type	Read-only
Reset	`0x-----00-`
Width	32

The following figure shows the bit assignments.

Figure 9-98 BASE register bit assignments

The following table shows the bit assignments.

Table 9-102 BASE register bit assignments

Bits Reset value Name Function

[31:12]

IMPLEMENTATION_DEFINED

BASEADDR

Base address of a ROM table. It points to the start of the debug register space or a ROM table address. Bits[11:0] of the address are 0x000 because the address is aligned to 4KB boundary. This field is valid only if BASE.EntryPresent bit is set to 1, in which case it returns the tie-off value of the input signal baseaddr[31:12], otherwise, it reads as 0x0.

[11:2]

0b0000000000

RAZ/WI

Read-As-Zero, Writes Ignored.

[1]

0b1

Format

Base address register format. Returns the value 0b1 indicating the ADIv5 format, which is unchanged in ADIv6.

[0]

IMPLEMENTATION_DEFINED

EntryPresent

This field indicates whether a debug component is present for this AP. It returns the tie-off value of the input signal baseaddr_valid.

0	No debug entry present.
1	Debug entry present and BASE.BASEADDR indicate the start address of the debug register space or ROM table.

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