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This register is the enable register for the interrupt signal. If the interrupt is enabled, the interrupt signal is asserted when the incoming AXI address transaction is not in the valid address range. It is writable only when CONTROL.ENABLE is clear and STATUS.READY is set. Disabling the CATU, that is setting the CONTROL.ENABLE register to 0, clears the interrupt signal.
The IRQEN register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-502 IRQEN register bit assignments
Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.