9 Interrupt enable register, IRQEN

This register is the enable register for the interrupt signal. If the interrupt is enabled, the interrupt signal is asserted when the incoming AXI address transaction is not in the valid address range. It is writable only when CONTROL.ENABLE is clear and STATUS.READY is set. Disabling the CATU, that is setting the CONTROL.ENABLE register to 0, clears the interrupt signal.

The IRQEN register characteristics are:

Attributes
Offset

0x000C

Type

Read-write

Reset

0x0000000-

Width

32

The following figure shows the bit assignments.

Figure 9-486 IRQEN register bit assignments
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The following table shows the bit assignments.

Table 9-502 IRQEN register bit assignments

Bits Reset value Name Function
[31:1] 0x0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[0] UNKNOWN IRQEN

Interrupt enable.

0

Interrupt is disabled.

1

Interrupt is enabled.

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