8 Cortex®‑R5 PIL debug memory map

The debug components in the Cortex®‑R5 PIL share memory space with the processor system.

The following tables show the locations of the Cortex‑R5 PIL CoreSight™ components.

Table 8-10 Cortex‑R5 PIL debug memory map

APB address range, PADDRDBG[16:0] Components
0x00000-0x00FFF ROM table.
0x10000-0x10FFF Cortex‑R5 processor0.
0x12000-0x12FFF Cortex‑R5 processor1, if present.
0x18000-0x18FFF CTI for processor0.
0x19000-0x19FFF CTI for processor1, if present.
0x1C000-0x1CFFF ETM for processor0, or shared ETM.
0x1D000-0x1DFFF ETM for processor1, if not shared.
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