9 Device Configuration Register, DEVID

This register is IMPLEMENTATION DEFINED for each Part Number and Designer. The register indicates the capabilities of the component.

The DEVID register characteristics are:

Attributes
Offset

0x0FC8

Type

Read-only

Reset

0x036-1-40

Width

32

The following figure shows the bit assignments.

Figure 9-396 DEVID register bit assignments
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The following table shows the bit assignments.

Table 9-409 DEVID register bit assignments

Bits Reset value Name Function
[31:29] 0b000 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[28:27] 0b00 CACHETYPE

Indicates the format of BUSCTL register bus control fields. Reads as 2'b00 indicating that AXICTL bus attribute bits [19:16] and [5:2] follow an implementation-defined non-generic format. See AXICTL register description.

[26:25] 0b01 MODES

Indicates the supported modes of operation. Reads as 2'b01 indicating that ETR supports CB, SWF1, and SWF2 modes.

[24] 0b1 NOSCAT

Indicates whether the scatter-gather mode is implemented. Fixed at 1 indicating that scatter-gather mode is not implemented.

[23:17] IMPLEMENTATION_DEFINED AXIAW

This field indicates the width of AXI address bus in ETR configuration. This field is valid only when DEVID.AXIAW_VALID is set. Possible values are:

0x20

32-bit AXI address buses.

0x28

40-bit AXI address buses.

0x2C

44-bit AXI address buses.

0x30

48-bit AXI address buses.

0x34

52-bit AXI address buses.

[16] 0b1 AXIAW_VALID

Indicates whether field DEVID.AW is valid. The value of this field is fixed at 1.

[15:14] 0b00 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[13:11] IMPLEMENTATION_DEFINED WBUF_DEPTH

Log2 of the number of write buffer entries. This value is set by the parameter WBUFFER_DEPTH. Each entry is of size ATB_DATA_WIDTH.

0x2

Depth of Write buffer is 4 entries.

0x3

Depth of Write buffer is 8 entries.

0x4

Depth of Write buffer is 16 entries.

0x5

Depth of Write buffer is 32 entries.

0x6

Depth of Write buffer is 64 entries.

0x7

Depth of Write buffer is 128 entries.

[10:8] IMPLEMENTATION_DEFINED MEMWIDTH

This value is equal to ATB_DATA_WIDTH.

0x2

Memory interface databus is 32-bits wide.

0x3

Memory interface databus is 64-bits wide.

0x4

Memory interface databus is 128-bits wide.

0x5

Memory interface databus is 256-bits wide.

[7:6] 0b01 CONFIGTYPE

Returns 0x1 indicating ETR configuration.

[5] 0b0 CLKSCHEME

RAM Clocking Scheme. This value indicates the TMC RAM clocking scheme used, that is, whether the TMC RAM operates synchronously or asynchronously to the TMC clock. Fixed to 0 indicating that TMC RAM clock is synchronous to the clk input.

[4:0] 0b00000 ATBINPORTCOUNT

Hidden Level of ATB input multiplexing. This value indicates the type/number of ATB multiplexing present on the input ATB. Fixed to 0x00 indicating that no multiplexing is present.

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