Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Arm® CoreSight™ System-on-Chip SoC-600 Technical Reference ManualRevision r3p0
Home > Programmers model > css600_tmc_ets introduction > Register descriptions > Integration Test ATB Control 1 Register, ITATBCTR1

9 Integration Test ATB Control 1 Register, ITATBCTR1

This register captures the value of the atid_s[6:0] input in integration mode. In functional mode, this register behaves as RAZ/WI. In integration mode, writes to this register are ignored and the reads return the value of atid_s input.

The ITATBCTR1 register characteristics are:

Attributes
Offset

0x0EF4
Type

Read-only
Reset

0x00000000
Width

32

The following figure shows the bit assignments.

Figure 9-424 ITATBCTR1 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-438 ITATBCTR1 register bit assignments

Bits Reset value Name Function
[31:7] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.
[6:0] 0b0000000 ATIDS

Returns the value of atid_s[6:0] input in integration mode.
Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved. 
Home > Programmers model > css600_tmc_ets introduction > Register descriptions > Integration Test ATB Control 1 Register, ITATBCTR1