8 Cortex-R5 PIL overview

A description of the Cortex®‑R5 Processor Integration Layer (PIL).

The Cortex‑R5 PIL integrates the Cortex‑R5 processor. The Cortex‑R5 processor might include one or two processors. The PIL also integrates:

All of the non-debug interfaces of the processor are exposed at the top-level of the PIL. The processor documentation describes these interfaces.

The Cortex‑R5 PIL has the following interfaces:

The PIL contains a single APB debug interface that can be asynchronous to the processor clock. It has one ATB trace output interface and an authentication interface. The following figure shows the Cortex‑R5 PIL.

Figure 8-5 Cortex‑R5 PIL block diagram
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


This section contains the following subsections:
Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.