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A description of the Cortex®‑R5 Processor Integration Layer (PIL).
The Cortex‑R5 PIL integrates the Cortex‑R5 processor. The Cortex‑R5 processor might include one or two processors. The PIL also integrates:
All of the non-debug interfaces of the processor are exposed at the top-level of the PIL. The processor documentation describes these interfaces.
The Cortex‑R5 PIL has the following interfaces:
The PIL contains a single APB debug interface that can be asynchronous to the processor clock. It has one ATB trace output interface and an authentication interface. The following figure shows the Cortex‑R5 PIL.