8 Cortex-R4 PIL overview

A description of the Cortex®‑R4 Processor Integration Layer (PIL).

The Cortex‑R4 PIL integrates the Cortex‑R4 processor with:

All of the non-debug interfaces of the processor are exposed at the top-level of the PIL. The address buses for the AXI-slave interface are 32 bits wide on the Cortex‑R4 PIL, but only 23 bits wide on the Cortex‑R4 processor. The PIL does not use the top nine bits of these buses. Other non-debug interfaces are the same as on the processor. The processor documentation describes these interfaces.

The Cortex‑R4 PIL has the following interfaces:

The PIL contains a single APB debug interface that can be asynchronous to the processor clock. It has one ATB trace output interface and an authentication interface. The following figure shows the Cortex‑R4 PIL.

Figure 8-4 Cortex‑R4 PIL block diagram
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This section contains the following subsections:
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