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Home > Programmers model > css600_jtagap introduction > Register descriptions > Control/Status Word register, CSW |
The CSW register configures and controls transfers through the JTAG interface to the connected memory system.
The CSW register characteristics are:
Offset |
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Type | Read-write |
Reset |
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Width | 32 |
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-144 CSW register bit assignments
Bits | Reset value | Name | Function | ||||
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[31] | 0b0 |
SERACTV | JTAG engine active. This bit gets set when the JTAG engine picks the first command from the Command FIFO for execution and remains set until all commands have been executed, that is until after CSW.WFIFOCNT becomes 0 and the JTAG engine goes to idle state.
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[30:28] | 0b000 |
WFIFOCNT | Command FIFO outstanding byte count. The reset value is |
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[27] | 0b0 |
RAZ/WI | Read-As-Zero, Writes Ignored. |
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[26:24] | 0b000 |
RFIFOCNT | Response FIFO outstanding byte count. The reset value is |
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[23:4] | 0x0 |
RAZ/WI | Read-As-Zero, Writes Ignored. |
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[3] | 0b0 |
PORTCONNECTED | PORT connected. This bit indicates the logical AND of port_connected inputs from all ports that are currently selected in the PSEL register. |
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[2] | 0b0 |
SRSTCONNECTED | SRST connected. This bit is logical AND of srst_connected inputs from all ports that are currently selected in PSEL register. |
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[1] | 0b0 |
TRST_OUT | This bit specifies the value to drive out on the active-LOW cs_ntrst pin for the ports that are connected, selected, and their PSTA bit is clear. This bit does not self-clear and must be cleared by a software write to this register.
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[0] | 0b0 |
SRST_OUT | This bit specifies the value to drive out on the active-LOW srst_out_n pin for the ports that are connected, selected, and their PSTA bit is clear. This bit does not self-clear and must be cleared by a software write to this register.
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