Arm CoreSight System-on-Chip SoC-600 Technical Reference Manual : 9 Control/Status Word register, CSW

9 Control/Status Word register, CSW

The CSW register configures and controls transfers through the JTAG interface to the connected memory system.

The CSW register characteristics are:

Attributes

Offset	`0x0D00`
Type	Read-write
Reset	`0x00000000`
Width	32

The following figure shows the bit assignments.

Figure 9-138 CSW register bit assignments

The following table shows the bit assignments.

Table 9-144 CSW register bit assignments

Bits Reset value Name Function

[31]

0b0

SERACTV

JTAG engine active. This bit gets set when the JTAG engine picks the first command from the Command FIFO for execution and remains set until all commands have been executed, that is until after CSW.WFIFOCNT becomes 0 and the JTAG engine goes to idle state.

0	JTAG engine is inactive.
1	JTAG engine is processing commands from the Command FIFO.

[30:28]

0b000

WFIFOCNT

Command FIFO outstanding byte count. The reset value is 0x0. Returns the number of command bytes held in the Command FIFO that are yet to be processed by the JTAG engine. Since the Command FIFO is 4 entries deep, this field can only take values between 0 and 4.

[27]

0b0

RAZ/WI

Read-As-Zero, Writes Ignored.

[26:24]

0b000

RFIFOCNT

Response FIFO outstanding byte count. The reset value is 0x0. Returns the number of bytes of response data held in the Response FIFO. Since the Response FIFO is 7 entries deep, this field can take any value between 0 and 7.

[23:4]

0x0

RAZ/WI

Read-As-Zero, Writes Ignored.

[3]

0b0

PORTCONNECTED

PORT connected. This bit indicates the logical AND of port_connected inputs from all ports that are currently selected in the PSEL register.

[2]

0b0

SRSTCONNECTED

SRST connected. This bit is logical AND of srst_connected inputs from all ports that are currently selected in PSEL register.

[1]

0b0

TRST_OUT

This bit specifies the value to drive out on the active-LOW cs_ntrst pin for the ports that are connected, selected, and their PSTA bit is clear. This bit does not self-clear and must be cleared by a software write to this register.

0	De-assert cs_ntrst HIGH.
1	Assert cs_ntrst LOW.

[0]

0b0

SRST_OUT

This bit specifies the value to drive out on the active-LOW srst_out_n pin for the ports that are connected, selected, and their PSTA bit is clear. This bit does not self-clear and must be cleared by a software write to this register.

0	De-assert srst_out_n HIGH.
1	Assert srst_out_n LOW.

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