Arm® CoreSight™ System-on-Chip SoC-600 Technical Reference Manual

Revision r3p2

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 About this product
1.2 Features
1.3 Supported standards
1.4 Documentation
1.5 Design process
1.6 Component list
1.7 Product revisions
2 DAP components functional description
2.1 Debug port
2.2 Memory Access Ports
2.2.1 APB Access Port
2.2.2 AHB Access Port
2.2.3 AXI Access Port
2.2.4 Error response handling
2.3 JTAG Access Port
2.4 Access Port v1 adapter
2.5 DP Abort replicator
2.6 DP Abort asynchronous bridge
2.7 DP Abort synchronous bridge
2.8 JTAG to SWJ adapter
2.9 SWJ to JTAG adapter
2.10 SWJ interconnect
3 APB infrastructure components functional description
3.1 APB interconnect
3.1.1 Arbitration
3.1.2 Error response
3.2 APB ROM table
3.3 APB asynchronous bridge
3.4 APB synchronous bridge
3.5 APB PADDRDBG31 adapter
3.6 APB3 to APB4 adapter
3.7 APB4 to APB3 adapter
4 AMBA Trace Bus infrastructure components functional description
4.1 ATB upsizer
4.2 ATB downsizer
4.3 ATB funnel
4.4 ATB replicator
4.5 ATB trace buffer
4.6 ATB asynchronous bridge
4.7 ATB synchronous bridge
4.8 Trace Memory Controller
4.8.1 TMC register access dependencies
4.8.2 Clock and reset
4.8.3 Interfaces
4.8.4 Operation
4.9 About the Trace Port Interface Unit
4.9.1 Clocks and resets
4.9.2 Functional interfaces
4.9.3 Trace out port
4.9.4 traceclk alignment
4.9.5 tracectl removal
4.9.6 tracectl encoding
4.9.7 Trace port triggers
4.9.8 Programming the TPIU for trace capture
4.9.9 Example configuration scenarios
4.9.10 TPIU pattern generator
4.10 CoreSight Address Translation Unit
4.10.1 CATU interfaces
4.10.2 Software interfaces
4.10.3 Initializing the CATU
4.10.4 Reprogramming the CATU
4.10.5 Error handling
4.10.6 Unpredictable behavior
5 Timestamp components functional description
5.1 Timestamp generator
5.2 Timestamp replicator
5.3 Timestamp interpolator
5.3.1 Functional interface
5.3.2 Low-Power Interface
5.3.3 Limitations
5.4 Narrow timestamp asynchronous bridge
5.4.1 Operation
5.4.2 Low-power features
5.4.3 Timestamp protection from slow clock
5.5 Narrow timestamp synchronous bridge
5.5.1 Operation
5.5.2 Low-power features
5.6 Narrow timestamp decoder
5.7 Narrow timestamp encoder
5.8 Narrow timestamp replicator
6 Embedded Cross Trigger components functional description
6.1 About cross triggering
6.2 Event signaling protocol
6.3 Cross Trigger Interface
6.3.1 asicctrl
6.4 Cross Trigger Matrix
6.5 Event Pulse to Event adapter
6.6 Event to Event Pulse adapter
6.7 Event Level asynchronous bridge
6.8 Event Level synchronous bridge
6.9 Event Pulse asynchronous bridge
6.10 Event Pulse synchronous bridge
6.11 Channel Pulse to Channel adapter
6.12 Channel to Channel Pulse adapter
6.13 Channel Pulse asynchronous bridge
6.14 Channel Pulse synchronous bridge
6.15 CTI to STM adapter
7 Authentication components functional description
7.1 Authentication replicator
7.2 Authentication asynchronous bridge
7.3 Authentication synchronous bridge
8 Processor Integration Layer components
8.1 Cortex-A5 PIL overview
8.1.1 Cortex-A5 PIL CoreSight component identification
8.1.2 Cortex-A5 PIL Debug memory map
8.2 Cortex-A8 PIL overview
8.2.1 Cortex-A8 PIL CoreSight component identification
8.2.2 Cortex-A8 PIL Debug memory map
8.3 Cortex-A9 PIL overview
8.3.1 Cortex-A9 PIL CoreSight component identification
8.3.2 Cortex-A9 PIL Debug memory map
8.4 Cortex-R4 PIL overview
8.4.1 Cortex-R4 PIL CoreSight component identification
8.4.2 Cortex-R4 PIL Debug memory map
8.5 Cortex-R5 PIL overview
8.5.1 Cortex-R5 PIL CoreSight component identification
8.5.2 Cortex-R5 PIL Debug memory map
8.6 Cortex-M0 PIL overview
8.6.1 Cortex-M0 PIL CoreSight component identification
8.6.2 Cortex-M0 PIL Debug memory map
8.7 Cortex-M3 PIL overview
8.7.1 Cortex-M3 PIL CoreSight component identification
8.7.2 Cortex-M3 PIL Debug memory map
8.8 Cortex-M4 PIL overview
8.8.1 Cortex-M4 PIL CoreSight component identification
8.8.2 Cortex-M4 PIL Debug memory map
9 Programmers model
9.1 Components programmers model
9.2 css600_dp introduction
9.2.1 Register summary
9.2.2 Register descriptions
9.3 css600_apbap introduction
9.3.1 Register summary
9.3.2 Register descriptions
9.4 css600_ahbap introduction
9.4.1 Register summary
9.4.2 Register descriptions
9.5 css600_axiap introduction
9.5.1 Register summary
9.5.2 Register descriptions
9.6 css600_apv1adapter introduction
9.6.1 Register summary
9.6.2 Register descriptions
9.7 css600_jtagap introduction
9.7.1 Register summary
9.7.2 Register descriptions
9.8 css600_apbrom introduction
9.8.1 Register summary
9.8.2 Register descriptions
9.9 css600_apbrom_gpr introduction
9.9.1 Register summary
9.9.2 Register descriptions
9.10 css600_atbfunnel_prog introduction
9.10.1 Register summary
9.10.2 Register descriptions
9.11 css600_atbreplicator_prog introduction
9.11.1 Register summary
9.11.2 Register descriptions
9.12 css600_tmc_etb introduction
9.12.1 Register summary
9.12.2 Register descriptions
9.13 css600_tmc_etf introduction
9.13.1 Register summary
9.13.2 Register descriptions
9.14 css600_tmc_etr introduction
9.14.1 Register summary
9.14.2 Register descriptions
9.15 css600_tmc_ets introduction
9.15.1 Register summary
9.15.2 Register descriptions
9.16 css600_tpiu introduction
9.16.1 Register summary
9.16.2 Register descriptions
9.17 css600_catu introduction
9.17.1 Register summary
9.17.2 Register descriptions
9.18 css600_tsgen introduction
9.18.1 Register summary
9.18.2 Register summary
9.18.3 Register descriptions
9.19 css600_cti introduction
9.19.1 Register summary
9.19.2 Register descriptions
A Revisions
A.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 01 March 2017 Non-Confidential First release for r0p0
0000-01 11 May 2017 Non-Confidential Second release for r0p0
0100-00 01 August 2017 Non-Confidential First release for r1p0
0200-00 08 December 2017 Non-Confidential First release for r2p0
0300-00 18 May 2018 Non-Confidential First release for r3p0
0301-00 30 April 2019 Non-Confidential First early access release for r3p1
0301-01 13 May 2019 Non-Confidential Second early access release for r3p1
0302-00 06 December 2019 Non-Confidential First early access release for r3p2

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