1.1 Introducing SVE

The ARM® Compiler toolchain supports targets that implement the Scalable Vector Extension (SVE) EAC (00rel2) for ARMv8-A AArch64.

SVE is the next-generation SIMD instruction set for AArch64, that introduces the following new architectural features for High Performance Computing (HPC):

  • Scalable vector length.
  • Per-lane predication.
  • Gather-load and scatter-store.
  • Fault-tolerant speculative vectorization.
  • Horizontal and serialized vector operations.

This release of the ARM Compiler toolchain lets you:

  • Assemble source code containing SVE instructions.
  • Disassemble ELF object files containing SVE instructions.
  • Compile C and C++ code for SVE-enabled targets, with an advanced auto-vectorizer capable of taking advantage of SVE features.
  • Use intrinsics to write SVE instructions directly from C code.

Note:

The ARM Compiler toolchain only supports bare-metal applications.

This document provides information about the features of the ARM Compiler toolchain that specifically relate to SVE. For information about the other features, see the ARM Compiler documentation.

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