3.2.2 Processor debug features

The processor obfuscated RTL and Cycle Model implement an example of the Cortex®-M3 processor integration level with preintegrated debug and trace components, and is configured for single core operation only.

The debug features include:

  • Serial Wire-JTAG Debug Access Port (SW-JTAG DAP), which is similar to standard Cortex-M3 implementation. This provides the external interface to the debug hardware on the FPGA board.
  • AHB-Debug Access Port (AHB-DAP), which provides access to processor registers and system memory.
  • Data Watchpoint and Trace (DWT) unit. This provides automated tracing of processor events.
  • Instrumentation Trace Macrocell (ITM). This allows limited and low overhead debug messaging, which is initialized by software.
  • Instruction-only Embedded Trace Macrocell (ETM). This allows for non-intrusive, full cycle, and accurate instruction trace.
  • A 4-pin Cortex-M processor optimized trace port supporting Single Wire Output protocol.

To use the 4-pin ETM trace mode of the Trace Port Interface Unit (TPIU), dedicated trace capture is required. You must connect to the trace port to observe the trace generated by the ETM. To implement an ETM in silicon, you are required to license it separately from ARM.

Since the debug configuration is fixed, only a simple connectivity test is provided for the Serial Wire configuration.

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