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The processor obfuscated RTL and Cycle Model implement an example of the Cortex®-M3 processor integration level with preintegrated debug and trace components, and is configured for single core operation only.
The debug features include:
To use the 4-pin ETM trace mode of the Trace Port Interface Unit (TPIU), dedicated trace capture is required. You must connect to the trace port to observe the trace generated by the ETM. To implement an ETM in silicon, you are required to license it separately from ARM.
Since the debug configuration is fixed, only a simple connectivity test is provided for the Serial Wire configuration.