3.2.1 Processor configuration

The processor obfuscated RTL and Cycle Model in Cortex®-M3 DesignStart™ Eval are configured to the following parameter values:

Table 3-1 Processor configuration parameter and values

Parameter Value Description
MPU_PRESENT 1 Memory Protection Unit (MPU) is present.

A tie-off pin allows this parameter to be hidden from software for emulating the performance of a design with no MPU.

NUM_IRQ 64 64 interrupts are supported.

Interrupt 45-63 are free. Other interrupts have default connections.

Note:

The full Cortex-M3 processor can support up to 240 interrupts.
LVL_WIDTH 3 Eight levels of interrupt priority are supported (3 bits of priority).
TRACE_LVL 3

The following trace components are present:

  • Embedded Trace Macrocell (ETM).
  • Instrumentation Trace Macrocell (ITM).
  • Data Watchpoint and Trace (DWT) unit.
  • Trace Port Interface Unit (TPIU).
  • AMBA AHB Trace Macrocell (HTM) interface. This can be used in FPGA for visibility of data accesses.

If you want to use the HTM to generate data trace, then you are required to license it from ARM.

DEBUG_LVL 3

Full debug functionality is supported, including data matching for watchpoint generation.

JTAG_PRESENT 1 Both JTAG and SWD are supported.
CLKGATE_PRESENT 0 Architectural clock gating is not supported, which results in better FPGA implementation.
RESET_ALL_REGS 0 Not all registers have a defined reset value. Only architecturally reset registers are explicitly reset.
OBSERVATION 0 The observation port is not present. The internal state of the processor is not observable.
WIC_PRESENT 1 The Wake-up Interrupt Controller (WIC) is present.
WIC_LINES 67 The WIC is sensitive to all interrupt events.
BB_PRESENT 1 The bit-banding feature is implemented.

Bit-banding enables every individual bit in the bit-banding region to be directly accessible for a word-aligned address.

For more information, see the ARM® Cortex®-M3 Technical Reference Manual.

CONST_AHB_CTRL 1 AHB-Lite compliance is ensured. This is recommended for best compatibility with peripherals.

For more information, see the ARM® AMBA® 3 AHB-Lite Protocol Specification (v1.0).

Note:

The processor in Cortex-M3 DesignStart Pro can be configured without restriction.
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