4.3.3 ZBT SSRAM signals

The following tables describe the signals for the ZBT SSRAMs:

Table 4-7 64-bit ZBT SSRAM1 connections

Signal Direction Description
SSRAM1_DQ[63:0] Input and output Data
SSRAM1_DQP[7:0] Input and output Parity data (not used)
SSRAM1_CLK[1:0] Output Clock
SSRAM1_A[20:0] Output Address
SSRAM1_nBW[7:0] Output Byte lane writes (active-LOW)
SSRAM1_nCE1 Output Chip select
SSRAM1_nWE Output Write enable (lower 32-bit, active-LOW)
SSRAM1_nCEN Output Write clock enable (active-LOW, tied to 0)
SSRAM1_nOE Output Output enable (active-LOW)
SSRAM1_MODE Output Not used (tied to 0)
SSRAM1_ADVnLD Output Not used (tied to 0)
SSRAM1_ZZ Output Not used (tied to 0)

Table 4-8 32-bit ZBT SSRAM2 connections

Signal Direction Description
SSRAM2_DQ[31:0] Input and output Data (byte lane #A)
SSRAM2_DQP[3:0] Input and output Parity data (not used)
SSRAM2_CLK Output Clock
SSRAM2_A[20:0] Output Address
SSRAM2_nBW[3:0] Output Byte lane writes (active-LOW)
SSRAM2_nCE1 Output Chip select
SSRAM2_nWE Output Write enable (lower 32-bit, active-LOW)
SSRAM2_nCEN Output Write clock enable (active-LOW, tied to 0)
SSRAM2_nOE Output Output enable (active-LOW)
SSRAM2_MODE Output Not used (tied to 0)
SSRAM2_ADVnLD Output Not used (tied to 0)
SSRAM2_ZZ Output Not used (tied to 0)

Table 4-9 32-bit ZBT SSRAM3 connections

Signal Direction Description
SSRAM3_DQ[31:0] Input and output Data (byte lane #A)
SSRAM3_DQP[3:0] Input and output Parity data (not used)
SSRAM3_CLK Output Clock (SSRAM1_CLK)
SSRAM3_A[20:0] Output Address
SSRAM3_nBW[3:0] Output Byte lane writes (active-LOW)
SSRAM3_nCE1 Output Chip select
SSRAM3_nWE Output Write enable (lower 32-bit, active-LOW)
SSRAM3_nCEN Output Write clock enable (active-LOW, tied to 0)
SSRAM3_nOE Output Output enable (active-LOW)
SSRAM3_MODE Output Not used (tied to 0)
SSRAM3_ADVnLD Output Not used (tied to 0)
SSRAM3_ZZ Output Not used (tied to 0)
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