4.2 Interrupt mapping

The following table describes the interrupt assignments in Cortex®-M3 DesignStart™ Eval:

Table 4-4 Interrupt assignments

INTISR bit Source Description
NMI Watchdog Watchdog
0 UART0 UART0 Tx and Rx combined
1 Reserved Unused
2 UART1 UART1 Tx and Rx combined
3 Reserved Reserved for APB slaves
4 Reserved Reserved for APB slaves
5 RTC Real Time Clock
6 GPIO0 Combined
7 GPIO1 Combined
8 Timer0 Timer0
9 Timer1 Timer1
10 Dual Timer Dual Timer
11 Reserved Reserved for APB slaves
12 UART 0/1/2/3/4 UART 0/1/2/3/4 overflow
13 Reserved Reserved for APB slaves
14 Reserved Unused
15 MPS2+ board Touch screen
16 GPIO0-0 GPIO0 pins
17 GPIO0-1 GPIO0 pins
18 GPIO0-2 GPIO0 pins
19 GPIO0-3 GPIO0 pins
20 GPIO0-4 GPIO0 pins
21 GPIO0-5 GPIO0 pins
22 GPIO0-6 GPIO0 pins
23 GPIO0-7 GPIO0 pins
24 GPIO0-8 GPIO0 pins
25 GPIO0-9 GPIO0 pins
26 GPIO0-10 GPIO0 pins
27 GPIO0-11 GPIO0 pins
28 GPIO0-12 GPIO0 pins
29 GPIO0-13 GPIO0 pins
30 GPIO0-14 GPIO0 pins
31 GPIO0-15 GPIO0 pins
32 Reserved Reserved for flash
33 Reserved Reserved for flash
34 Reserved Reserved for Cordio BT4
35 Reserved Reserved for Cordio BT4
36 Reserved Reserved for Cordio BT4
37 Reserved Reserved for Cordio BT4
38 Reserved Reserved for Cordio BT4
39 Reserved Reserved for Cordio BT4
40 Reserved Reserved for Cordio BT4
41 Reserved Reserved for Cordio BT4
42 GPIO2 Combined
43 GPIO3 Combined
44 TRNG True Random Number Generator
45 UART2 Combined Tx and Rx
46 UART3 Combined Tx and Rx
47 Ethernet Ethernet interrupt
48 I2S I2S interrupt
49 MPS2 SPI0 SPI header interrupt
50 MPS2 SPI1 CLCD SPI interrupt
51 MPS2 SPI2 ADC for Shield
52 MPS2 SPI3 Shield0 SPI
53 MPS2 SPI4 Shield1 SPI
54 GPIO4 Combined
55 GPIO5 Combined
56 UART4 Tx and Rx combined
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