4.3.2 Debug and trace signals

The following table displays the debug and trace signals:

Table 4-6 Debug and trace signals

Signal Direction Description
CS_TDI Input JTAG Test Data Input
CS_TCK Input Serial Wire Debug clock or JTAG clock.
CS_TMS Input and output Serial Wire Debug I/O or JTAG Test Mode Select.
CS_TDO Output SWV or JTAG Test Data Output.
CS_nSRST Input Not required for Cortex®-M.
CS_TRACECLK Output Trace clock
CS_TRACECTL Output Trace control
CS_TRACEDATA[15:0] Output Trace data. Only pins [3:0] are used by Cortex-M3 processor.
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